GTL2005 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS GTL2005 Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator Product specification Supersedes data of 1999 Jun 23 1999 Sep 17 Philips Semiconductors Philips Semiconductors Product specification Quad GTL/GTL+ to LVTTL/TTL bidirectional non-latched translator Features - Operates as a quad GTL/GTL+ sampling receiver or as a - Quad bidirectional bus interface - Live insertion/extraction permitted - Latch-up protection exceeds 500 m A per JESD78 - ESD protection exceeds 2000 V HBM per JESD22-A114, and 1000 V CDM per JESD22-CC101 LVTTL/TTL to GTL/GTL+ driver PIN CONFIGURATION DIR 1 A0 2 A1 3 GTLREF 4 A2 5 A3 6 14 VCC 13 B0 12 B1 11 GND 10 B2 9 B3 8 GND DESCRIPTION The GTL2005 is a quad translating transceiver designed for 3.3 V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. GND 7 SW00321 QUICK REFERENCE DATA SYMBOL t PLH t PHL CIN CI/O PARAMETER Propagation delay An to Bn or Bn to An Input capacitance DIR I/O pin capacitance CONDITIONS Tamb = 25°C CL = 50 p F; VCC = 3.3 V VI = 0 V or VCC Outputs disabled; VI/O = 0 V or 3.0 V TYPICAL B to A A to B 2.1 1.9 3.0 7.8 4.1 4.3 3.0 4.5 UNIT ns p F p F ORDERING INFORMATION PACKAGES 14-Pin Plastic TSSOP Type II TEMPERATURE RANGE - 40°C to +85°C ORDER CODE GTL2005 PW DH DWG NUMBER SOT402-1 PIN DESCRIPTION PIN NUMBER 1 2, 3, 5, 6 13, 12, 10, 9 4 7, 8, 11 14 SYMBOL DIR A0 - A3 B0 - B3 GTLREF GND VCC NAME AND FUNCTION Direction control input Data inputs/outputs (A side, GTL) Data inputs/outputs (B side, TTL) GTL reference voltage Ground (0 V) Positive supply voltage LOGIC...