GTL2004 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS GTL2004 Quad GTL/GTL+ to LVTTL/TTL bidirectional latched translator Product specification Supersedes data of 1999 May 15 1999 Jul 19 Philips Semiconductors Philips Semiconductors Product specification Quad GTL/GTL+ to LVTTL/TTL bidirectional latched translator Features - Operates as a quad GTL/GTL+ sampling receiver or as a - Quad bidirectional bus interface - Separate latch enable for each bit - Live insertion/extraction permitted - B outputs include 30Ω series resistance - Latch-up protection exceeds 500m A per JEDEC Std 17 - ESD protection exceeds 2000V per JEDEC Std DESCRIPTION The GTL2004 is a quad translating transceiver designed for 3.3V system interface with a GTL/GTL+ bus. The direction pin allows the part to function as either a GTL to TTL sampling receiver or as a TTL to GTL interface. Separate latch enables allow sampling and holding of data from the GTL bus. LVTTL/TTL to GTL/GTL+ driver PIN CONFIGURATION A0 1 16 VCC LE0 2 A1 3 LE1 4 A2 5 LE2 6 A3 7 GND 8 15 DIR 14 B0 13 B1 12 B2 11 B3 10 GTLREF 9 LE3 SW00318 PIN DESCRIPTION PIN NUMBER 15 1, 3, 5, 7 11, 12, 13, 14 2, 4, 6, 9 10 8 16 SYMBOL DIR A0 - A3 B0 - B3 LE0 - LE3 GTLREF GND VCC NAME AND FUNCTION Direction control input Data inputs/outputs (A side, GTL) Data inputs/outputs (B side, TTL) Latch enables GTL reference voltage Ground (0V) Positive supply voltage QUICK REFERENCE DATA SYMBOL t PLH t PHL CIN CI/O PARAMETER Propagation delay An to Bn or Bn to An Input capacitance DIR, LEn I/O pin capacitance CONDITIONS Tamb = 25°C CL = 50p F; VCC = 3.3V VI = 0V or VCC Outputs disabled; VI/O = 0V or 3.152V TYPICAL UNIT B to A 2.0 1.8 3.0 7.2 A to B 4.4 4.7 3.0 4.6 ns p F p...