P5010 Description
Freescale Semiconductor Data Sheet: Technical Data QorIQ P5020/P5010 Data Sheet Document Number: 1, 03/2015 P5020/P5010 FC-PBGA 1295 37.5 mm × 37.5 mm The P5020 and P5010 QorIQ integrated munication processor bines Power Architecture® processor cores with high-performance data path acceleration logic and network and peripheral bus interfaces required for networking, tele/data, wireless infrastructure, and aerospace...
P5010 Key Features
- Two e5500 Power Architecture cores (one on the P5010)
- Each core has a backside 512-Kbyte L2 Cache with ECC
- Three levels of instructions: User, Supervisor, and Hypervisor
- Independent boot and reset
- Secure boot capability
- CoreNet fabric supporting coherent and non-coherent transactions amongst CoreNet endpoints
- 2-Mbyte CoreNet platform cache with ECC (one on the P5010)
- One 10-Gigabit Ethernet (XAUI) controller
- Five 1-Gigabit Ethernet controllers
- 1 Gb/s SGMII, 2.5 Gb/s SGMII and RGMII interfaces