PMN55LN Datasheet | NXP Semiconductors

Description N-channel enhancement mode field-effect transistor in a plastic package using Trench MOS™ technology. Product availability: PMN55LN in SOT457 (TSOP6). 1.2 Features s Low on-state resistance in small surface mount package. 1.3 Applications s DC-to-DC primary side. 1.4 Quick reference data s VDS ≤ 20 V s Ptot ≤ 1.75 W s ID ≤ 4.1 A s RDSon ≤ 65 mΩ 2. Pinning information Table 1: Pin 1,2,5,6 3 4 Pinning - SOT457 (TSOP6), simplified outline and symbol Description drain (d) gate (g) source (s) g s 6 5 4 d Simplified outline Symbol 1 Top view MBK092 MBB076 SOT457 (TSOP6) Philips Semiconductors µTrench MOS™ logic level FET 3. Limiting values Table 2: Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter VDS VDGR VGS ID IDM Ptot Tstg Tj IS ISM drain-source voltage (DC) drain-gate voltage (DC) gate-source voltage (DC) drain current (DC) peak drain current total power dissipation storage temperature junction temperature source (diode forward) current (DC) Tsp = 25 °C peak source (diode forward) current Tsp = 25 °C; pulsed; tp ≤ 10 µs Tsp = 25 °C; VGS = 10 V; Figure 2 and 3 Tsp = 100 °C; VGS = 10 V; Figure 2 Tsp = 25 °C; pulsed; tp ≤ 10 µs; Figure 3 Tsp = 25 °C; Figure 1 Conditions 25 °C ≤ Tj ≤ 150 °C 25 °C ≤ Tj ≤ 150 °C; RGS = 20 kΩ Min - 55 - 55 Max 20 20 ±15 4.1 2.6 16.5 1.75 +150 +150 1.45 5.95 Unit V V V A A A W °C °C A A Source-drain diode 9397 750 10937 © Koninklijke Philips Electronics N.V. 2003. All rights reserved. Product data Rev. 01 - 24 March 2003 2 of 12 Philips Semiconductors µTrench MOS™ logic level FET 120 Pder (%) 80 03aa17 120 Ider (%) 80 03aa25 0 0 50 100 150 Tsp (°C) 200 0 0 50 100 150 200 Tsp (°C) P tot P der = ---------------------- × 100 % P ° tot ( 25 C...