SSTU32866 Datasheet | NXP Semiconductors

Rev. 01 - 09 July 2004 .. 1.8 V 25-bit 1:1 or 14-bit 1:2 configurable registered buffer with parity for DDR2 RDIMM applications Objective data 1. Description The SSTU32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a patible pinout. The JEDEC standard for SSTU32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1:1 or 14-bit 1:2, and in the latter configuration can be...