SSTU32865 - 28-bit 1:2 registered buffer

The SSTU32865 is a 1.8 V 28-bit 1:2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules.

• s 28-bit data register supporting DDR2 s Fully compliant to JEDEC standard JESD82-9 s Supports 2 rank by 4 DIMM density by integrating equivalent functionality of two JEDEC-standard DDR2 registers (i. e. 2 × SSTU32864 or 2 × SSTU32866) s Parity checking function across 22 input data bits s Parity out signal s Controlled output impedance drivers enable optimal signal integrity and speed s Exceeds JESD82-9 speed performance (1.8 ns max. single-bit switching propagation delay, 2.0 ns max. mass-switc.