Full PDF Text Transcription for SSTUB32866 (Reference)
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SSTUB32866. For precise diagrams, and layout, please refer to the original PDF.
www.DataSheet4U.com SSTUB32866 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev. 02 — 9 October 2006 Produ...
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parity for DDR2-800 RDIMM applications Rev. 02 — 9 October 2006 Product data sheet 1. General description The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUB32866 registered buffer. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM.
SSTUB32866 Datasheet
