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TZA3005H - SDH/SONET STM1/OC3 and STM4/OC12 transceiver

Description

The TZA3005H SDH/SONET transceiver chip is a fully integrated serialization/deserialization STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) interface device.

Features

  • Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s).
  • Supports reference clock frequencies of 19.44, 38.88, 51.84 and 77.76 MHz.
  • Meets Bellcore, ANSI and ITU-T specifications.
  • Meets ITU jitter specification typically to a factor of 2.5.
  • Integral high-frequency PLL for clock generation.
  • Interface to TTL logic.
  • Low jitter PECL (Positive Emitter Coupled Logic) interface.
  • 4 or 8-bit STM1/OC3 TTL data path.

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Datasheet Details

Part number TZA3005H
Manufacturer NXP
File Size 127.17 KB
Description SDH/SONET STM1/OC3 and STM4/OC12 transceiver
Datasheet download datasheet TZA3005H Datasheet
Additional preview pages of the TZA3005H datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS DATA SHEET TZA3005H SDH/SONET STM1/OC3 and STM4/OC12 transceiver Product specification Supersedes data of 1997 Aug 05 File under Integrated Circuits, IC19 2000 Feb 17 Philips Semiconductors Product specification SDH/SONET STM1/OC3 and STM4/OC12 transceiver FEATURES • Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) • Supports reference clock frequencies of 19.44, 38.88, 51.84 and 77.76 MHz • Meets Bellcore, ANSI and ITU-T specifications • Meets ITU jitter specification typically to a factor of 2.
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