TZA3005H Datasheet | NXP Semiconductors

FEATURES - Supports STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) - Supports reference clock frequencies of 19.44, 38.88, 51.84 and 77.76 MHz - Meets Bellcore, ANSI and ITU-T specifications - Meets ITU jitter specification typically to a factor of 2.5 - Integral high-frequency PLL for clock generation - Interface to TTL logic - Low jitter PECL (Positive Emitter Coupled Logic) interface - 4 or 8-bit STM1/OC3 TTL data path - 4 or 8-bit STM4/OC12 TTL data path - No external filter ponents required - QFP64 package - Diagnostic and line loopback modes - Lock detect - LOS (Loss of Signal) input - Low power (0.9 W typical) - Selectable frame detection and byte realignment - Loop timing - Forward and reverse clocking - Squelched clock operation - Self-biased PECL inputs to support AC coupling. APPLICATIONS - SDH/SONET modules - SDH/SONET-based transmission systems - SDH/SONET test equipment - ATM (Asynchronous Transfer Mode) over SDH/SONET - Add drop multiplexers - Broadband cross-connects - Section repeaters - Fibre optic test equipment - Fibre optic terminators. ORDERING INFORMATION TYPE NUMBER TZA3005H PACKAGE NAME QFP64 DESCRIPTION plastic quad flat package; 64 leads (lead length 1.6 mm); body 14 × 14 × 2.7 mm GENERAL DESCRIPTION The TZA3005H SDH/SONET transceiver chip is a fully integrated serialization/deserialization STM1/OC3 (155.52 Mbits/s) and STM4/OC12 (622.08 Mbits/s) interface device. It performs all necessary serial-to-parallel and parallel-to-serial functions in accordance with SDH/SONET transmission standards. It is suitable for SONET-based applications and can be used in conjunction with the data and clock recovery unit (TZA3004), optical front-end (TZA3023 with TZA3034/44) and a laser driver (TZA3001). A typical network application is shown in Fig.10. A high-frequency phase-locked loop is used for on-chip clock synthesis, which allows a slower external transmit reference clock to be used. A reference clock of 19.44, 38.88, 51.84 or...