UJA1163
description
The UJA1163 is a mini high-speed CAN System Basis Chip (SBC) containing an ISO 11898-2/5 pliant HS-CAN transceiver and an integrated 5 V/100 m A supply for a microcontroller. The UJA1163 can be operated in a very low-current Standby mode with bus wake-up capability and supports ISO 11898-6 pliant autonomous CAN biasing.
The UJA1163 implements the standard CAN physical layer as defined in the current ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898 including CAN FD, additional timing parameters defining loop delay symmetry are included. This implementation enables reliable munication in the CAN FD fast phase at data rates up to 2 Mbit/s.
2. Features and benefits
2.1 General
- ISO 11898-2 and ISO 11898-5 pliant high-speed CAN transceiver
- Loop delay symmetry timing enables reliable munication at data rates up to
2 Mbit/s in the CAN FD fast phase
- Autonomous bus biasing according to ISO 11898-6
- Fully integrated 5 V/100 m A low-drop...
