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UJA1163 - Mini high-speed CAN system

General Description

The UJA1163 is a mini high-speed CAN System Basis Chip (SBC) containing an ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a microcontroller.

Key Features

  • 2.1 General.
  • ISO 11898-2 and ISO 11898-5 compliant high-speed CAN transceiver.
  • Loop delay symmetry timing enables reliable communication at data rates up to 2 Mbit/s in the CAN FD fast phase.
  • Autonomous bus biasing according to ISO 11898-6.
  • Fully integrated 5 V/100 mA low-drop voltage regulator for 5 V microcontroller supply (V1).
  • Bus connections are truly floating when power to pin BAT is off 2.2 Designed for automotive.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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UJA1163 Mini high-speed CAN system basis chip with Standby mode Rev. 2 — 17 April 2014 Product data sheet 1. General description The UJA1163 is a mini high-speed CAN System Basis Chip (SBC) containing an ISO 11898-2/5 compliant HS-CAN transceiver and an integrated 5 V/100 mA supply for a microcontroller. The UJA1163 can be operated in a very low-current Standby mode with bus wake-up capability and supports ISO 11898-6 compliant autonomous CAN biasing. The UJA1163 implements the standard CAN physical layer as defined in the current ISO11898 standard (-2 and -5). Pending the release of the updated version of ISO11898 including CAN FD, additional timing parameters defining loop delay symmetry are included.