UM10430 Description
20151210 LPC18xx user manual Fixed formatting issues. See Table 90 “CREG1 register (CREG1, address 0x4004 3008) bit description”. Updated text in Section 12.2.1 “Configuring the BASE_M3_CLK for high operating frequencies”:.
UM10430 Key Features
- Added the line to the remark in Section 10.4.10 “USB0 frame length adjust register” and
- Fixed typographical error in Section 6.2 “Features”: Cipher-Block chaining
- Added the paragraph: The Motor control PWM is not available on LPC1810FET100
- Added 0x10 to all the offsets for exception numbers 53 and above ending with 0x110 for the QEI
- Added device and hex coding information for S parts to Table 40 “LPC18xx part identification
- Fixed CBC to read Cipher Block Chaining instead of Cipher Book Chaining in Section 8.2 “Features”
- Updated Section 28.6 “Register description”text. Was REGMODEn = 1: Registers operate as match