N02L163WN1A Datasheet PDF (Ultra-Low Power Asynchronous CMOS SRAM)

General Description

Pin Name A0-A16 WE CE OE LB UB I/O0-I/O15 NC VCC VSS Pin Function Address Inputs Write Enable Input Chip Enable Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs Not Connected Power Ground (DOC# 14-02-014 REV L ECN# 01-1000) The specifications of this de

Key Features

Single Wide Power Supply Range 2.3 to 3.6 Volts.
Very low standby current 2.0µA at 3.0V (Typical).
Very low operating current 2.0mA at 3.0V and 1µs (Typical).
Very low Page Mode operating current 0.8mA at 3.0V and 1µs (Typical).
Simple memory control Single Chip Enable (CE) Byte control for independent byte operation Output Enable (OE) for memory expansion.
Low voltage data retention Vcc = 1.8V.
Very fast output enable access time 3.

Datasheet Details

Part number	N02L163WN1A
Manufacturer	NanoAmp Solutions
File Size	294.69 KB
Description	Ultra-Low Power Asynchronous CMOS SRAM
Datasheet	N02L163WN1A Datasheet

Part number

N02L163WN1A

Manufacturer

NanoAmp Solutions

File Size

294.69 KB

Description

Ultra-Low Power Asynchronous CMOS SRAM

Datasheet

N02L163WN1A Datasheet

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text

NanoAmp Solutions, Inc. 1982 Zanker Road, San Jose, CA 95112 ph: 408-573-8878, FAX: 408-573-8877 www.nanoamp.com N02L163WN1A www.DataSheet4U.com 2Mb Ultra-Low Power Asynchronous CMOS SRAM 128K × 16bit Overview The N02L163WN1A is an integrated memory device containing a 2 Mbit Static Random Access Memory organized as 131,072 words by 16 bits. The device is designed and fabricated using NanoAmp’s advanced CMOS technology to provide both high-speed performance and ultra-low power. The device operates with a single chip enable (CE) control and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently.