Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits.
It is internally configured as a quad-bank DRAM.
Read or Write command are used to select the bank and the starting column location for the burst access.
Features
- CAS Latency and Frequency
Maximum Operating Frequency (MHz).
- DDR333 DDR300 (-6) (-66) 2 133 133 2.5 166 150.
- Values are nominal (exact tCK should be used). CAS Latency.
- Double data rate architecture: two data transfers per clock cycle.
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
- DQS is edge-aligned with data for reads and is centeraligned with data for writes.
- Differential clock.
NT5DS32M4AW Datasheet
