NT5DS32M8AT - 256Mb DDR333/300 SDRAM

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Nanya

Part number	NT5DS32M8AT
Manufacturer	Nanya
File Size	569.21 KB
Description	256Mb DDR333/300 SDRAM
Datasheet	NT5DS32M8AT Datasheet
Additional preview pages of the NT5DS32M8AT datasheet.

The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits.

It is internally configured as a quad-bank DRAM.

The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations.

CAS Latency and Frequency CAS Latency 2 2.5 Maximum Operating Frequency (MHz).
DDR333 (-6) DDR300 (-66) 133 133 166 150.
Double data rate architecture: two data transfers per clock cycle.
Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver.
DQS is edge-aligned with data for reads and is centeraligned with data for writes.
Differential clock inputs (CK and CK).
Four internal banks for.

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Published: Sep 24, 2006 |