NT5DS32M8CS Overview
They are all based on Nanya’s 110 nm design process. Read or Write mand are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations.
NT5DS32M8CS Key Features
- DDR 256M bit, die C, based on 110nm design rules
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes
