NT5DS32M8BW Description
The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4, or 8 locations.
NT5DS32M8BW Key Features
- (-75B) 2 133 100 2.5 166 133
- 6K also meets DDR266A Spec (MHz-CL-tRCD-tRP = 133-2-3-3) CAS Latency
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes