NT5DS128M4CS Datasheet | Nanya Techology

NT5DS32M16CG NT5DS64M8CG NT5DS128M4CG NT5DS32M16CS NT5DS64M8CS NT5DS128M4CS 512Mb DDR SDRAM Features - DDR 512M bit, Die C, based on 90nm design rules - Double data rate architecture: two data transfers per clock cycle - Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - DQS is edge-aligned with data for reads and is centeraligned with data for writes - Differential clock inputs (CK and CK) - Four internal banks for concurrent operation - Data mask (DM) for write data - DLL aligns DQ and DQS transitions with CK transitions - mands entered on each positive CK edge; data and data mask referenced to both edges of DQS -...