Datasheet Summary
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NT5DS64M4BT NT5DS32M8BT NT5DS16M16BT
NT5DS64M4BF NT5DS32M8BF NT5DS16M16BF
NT5DS64M4BS NT5DS32M8BS NT5DS16M16BS
NT5DS64M4BG NT5DS32M8BG NT5DS16M16BG
256Mb DDR SDRAM Features
CAS Latency and Frequency
CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166
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- - Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes
- Differential clock inputs (CK and CK)
Four internal banks for concurrent operation Data mask (DM)...