NT5CB256M16CP Datasheet | Nanya

Features - JEDEC DDR3 pliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/ ) - Double-data rate on DQs, DQS and DM - Signal Integrity - Configurable DS for system patibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) - Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes - Signal Synchronization - Write Leveling via MR settings - Read Leveling via MPR - Power Saving Mode - Partial Array Self Refresh (PASR) - Power Down Mode - Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_135 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.1V) Options - Speed Grade (CL-TRCD-TRP) - 2133 Mbps / 14-14-14 - 1866 Mbps / 13-13-13 - 1600 Mbps / 11-11-11 2,3 - Temperature Range (Tc) - mercial Grade = 0℃ ~95℃ - Industrial Grade = -40℃ ~95℃ - Automotive Grade 2 = -40℃ ~105℃ - Automotive Grade 3 = -40℃ ~95℃ Programmable Functions - - - - - - CAS Latency (5/6/7/8/9/10/11/12/13/14) CAS Write Latency (5/6/7/8/9/10) Additive Latency (0/CL-1/CL-2) Write Recovery Time (5/6/7/8/10/12/14/16) Burst Type (Sequential/Interleaved) Burst Length (BL8/BC4/BC4 or 8 on the fly) - -...