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NT5CB256M16ER - Commercial and Industrial DDR3 4Gb SDRAM

Download the NT5CB256M16ER datasheet PDF. This datasheet also covers the NT5CC512M8EQ variant, as both devices belong to the same commercial and industrial ddr3 4gb sdram family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
  • Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
  • Power Saving Mode - Power Down Mode.
  • Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%).
  • Signal Synchroniza.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (NT5CC512M8EQ-Nanya.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number NT5CB256M16ER
Manufacturer Nanya
File Size 3.35 MB
Description Commercial and Industrial DDR3 4Gb SDRAM
Datasheet download datasheet NT5CB256M16ER Datasheet

Other Datasheets by Nanya

Part Number Description
NT5CB256M16BP 4Gb DDR3 SDRAM B-Die
NT5CB256M16CP Industrial and Automotive DDR3(L) 4Gb SDRAM
NT5CB256M16DP Industrial and Automotive DDR3(L) 4Gb SDRAM
NT5CB256M4AN 1Gb DDR3 SDRAM A-Die
NT5CB256M8BN 2Gb DDR3 SDRAM B-Die
NT5CB256M8DN 2Gb DDR3 SDRAM D-Die
NT5CB256M8FN Industrial and Automotive DDR3(L) 2Gb SDRAM
NT5CB256M8GN 2Gb DDR3 SDRAM G-Die
NT5CB256M8IN Industrial and Automotive DDR3(L) 2Gb SDRAM
NT5CB256M8JQ Commercial and Industrial DDR3(L) 2Gb SDRAM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DDR3-4Gb E-Die NT5CB(C)512M8EQ/NT5CB(C)256M16ER Commercial and Industrial DDR3(L) 4Gb SDRAM Features  Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM  Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes  Power Saving Mode - Power Down Mode  Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%)  Signal Synchronization - Write Leveling via MR settings 5 - Read Leveling via MPR  Interface and Power Supply - SSTL_15 for DDR3:VDD/VDDQ=1.5V(±0.075V) - SSTL_1352 for DDR3L:VDD/VDDQ=1.35V(-0.067/+0.