Datasheet Details
| Part number | NT5CC256M8FN |
|---|---|
| Manufacturer | Nanya |
| File Size | 3.26 MB |
| Description | Industrial and Automotive DDR3(L) 2Gb SDRAM |
| Datasheet |
 NT5CC256M8FN Datasheet
|
|
|
General Description
The 2Gb Double-Data-Rate-3 (DDR3(L)) is double data rate architecture to achieve high-speed operation.
It is internally configured as an eight bank DRAMs.
The 2Gb chip is organized as 32Mbit x 8 I/Os x 8 banks or 16Mbit x 16 I/Os x 8 bank devices.
Key Features
- JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
- Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%).
- Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
- Signal Synchronization - Write Leveling via MR settings - R.