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54ABT16500 - 18-Bit Universal Bus Transceivers

General Description

These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes.

Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs.

Key Features

  • n Combines D-Type latches and D-Type flip-flops for operation in transparent, latched, or clocked mode n Flow-through architecture optimizes PCB layout n Guaranteed latch-up protection n High impedance glitch free bus loading during entire power up and power down cycle n Non-destructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9687001 Ordering Code Military 54ABT16500W-QML Package Number WA56A 56-Lead Cerpack Package.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE Outputs 54ABT16500 July 1998 54ABT16500 18-Bit Universal Bus Transceivers with TRI-STATE ® Outputs General Description These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB is held at a high or low logic level. If LEAB is low, the A bus data is stored in the latch/flip-flop on the high-to-low transition of CLKAB. Output-enable OEAB is active-high.