GENERAL DESCRIPTION
n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) — 5962-9318801 FEATURES
n Output sink capability of 48 mA, source capability of 24 mA Ordering Code Military 54ABT240J-QML 54ABT240W-QML 54ABT240E-QML Package Number J20A W20A E20A Package DESCRIPTION
20-Lead Ceramic Dual-In-Line 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Connection Diagrams Pin Assignment for DIP and Flatpak Pin Assignment for LCC DS100202-2 DS100202-1 Pin Names OE1, OE2 I0–I7 O0–O7 DESCRIPTION
TRI-STATE Output Enable Inputs Inputs Outputs TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100202 Truth Tables Inputs OE1 L L H Inputs OE2 L L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance In L H X Outputs (Pins 12, 14, 16, 18) H L Z Out...
National Semiconductor
