GENERAL DESCRIPTION
FEATURES
n Non-inverting buffers n Output sink capability of 48 mA, source capability of 24 mA n Guaranteed latchup protection n High impedance glitch free bus loading during entire power up and power down cycle n Nondestructive hot insertion capability n Standard Microcircuit Drawing (SMD) 5962-9322701 Ordering Code Military 54ABT241J-QML 54ABT241W-QML 54ABT241E-QML Package Number J20A W20A E20A 20-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier, Type C Pin Names OE1 OE2 I0–I7 O0–O7 DESCRIPTION
Output Enable Input (Active Low) Output Enable Input (Active High) Inputs Outputs Package DESCRIPTION
20-Lead Ceramic Dual-In-Line Connection Diagram Pin Assignment for DIP and Cerpack Truth Table OE1 H L L I0–3 X H L O0–3 Z H L OE2 L H H I4–7 X H L O4–7 Z H L H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial Z = High Impedance DS100215-1 Pin Assignment for LCC DS100215-4 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100215 1 PrintDate=1998/07/13 PrintTime=19:04:09 43584 ds100215 Rev.
National Semiconductor
