ADC10040
Description
The ADC10040 is a monolithic CMOS analog-to-digital converter capable of converting analog input signals into 10-bit digital words at 40 Megasamples per second (MSPS). This converter uses a differential, pipeline architecture with digital error correction and an on-chip sample-and-hold circuit to provide a complete conversion solution, and to minimize power consumption, while providing excellent dynamic performance.
Key Features
- Single +3.0V operation
- Selectable 2.0 VP-P, 1.5 VP-P, or 1.0 VP-P full-scale input swing
- 400 MHz -3 dB input bandwidth
- Low power consumption
- Standby mode
- On-chip reference and sample-and-hold amplifier
- Offset binary or two’s complement data format
- Separate adjustable output driver supply to accommodate 2.5V and 3.3V logic families
- 28-pin TSSOP package Key Specifications n n n n n n n n
- Resolution Conversion Rate Full Power Bandwidth DNL SNR (fIN = 11 MHz) SFDR (fIN = 11 MHz) Data Latency Supply Voltage Power Consumption, 40 MHz 10 Bits 40 MSPS 400 MHz ± 0.3 LSB (typ) 59.6 dB (typ) -80 dB (typ) 6 Clock Cycles +3.0V 55.5 mW
