ADC14C095 Datasheet | National Semiconductor

Description NOTE: This is Advance Information for products currently in development. ALL specifications are design targets and are subject to change. The ADC14C065, ADC14C080, ADC14C095, and ADC14105 are high-performance CMOS analog-to-digital converters capable of converting analog input signals into 14-bit digital words at rates up to 65/80/95/105 Mega Samples Per Second (MSPS) respectively. These converters use a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external ponent count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1 GHz. The ADC14C065/080/095/105 may be operated from a single +3.3V power supply and consumes low power. A separate +2.5V supply may be used for the digital output interface which allows lower power operation with reduced noise. A power-down feature reduces the power consumption to very low levels while still allowing fast wake-up time to full operation. The differential inputs provide a 2V full scale differential input swing. A stable 1.2V internal voltage reference is provided, or the ADC14C065/080/095/105 can be operated with an external 1.2V reference. Output data format (offset binary versus 2’s plement) and duty cycle stabilizer are pin-selectable. The duty cycle stabilizer maintains performance over a wide range of clock duty cycles. The ADC14C065/080/095/105 is available in a 32-lead LLP package and operates over the industrial temperature range of - 40˚C to +85˚C. Features n n n n n n n n n n 1 GHz Full Power Bandwidth Internal sample-and-hold circuit Low power consumption Internal precision reference Data Ready output clock Clock Duty Cycle Stabilizer Single +3.3V supply operation Power-down mode Offset binary or 2’s plement output data format 32-pin LLP package, (5x5x0.8mm, 0.5mm pin-pitch) Key Specifications n n n n n n n For ADC14C105 Resolution Conversion Rate SNR...