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CD40192BM - Synchronous 4-Bit Up/Down Decade Counter

General Description

These up down counters are monolithic complementary MOS (CMOS) integrated circuits The CD40192BM and CD40192BC are BCD counters while the CD40193BM and CD40193BC are binary counters Counting up and counting down is performed by two count inputs one being held high while the other is clocked The outp

Key Features

  • Y Y Y Wide supply voltage range High noise immunity Low power TTL compatibility Y Y Y 3V to 15V 0 45 VDD (typ ) Fan out of 2 driving 74L or 1 driving 74LS Carry and borrow outputs for easy expansion to N-bit by cascading Asynchronous clear Equivalent to MM54C192 MM74C192 and MM54C193 MM74C193 Connection Diagram Dual-In-Line Package Order Number CD40192B or CD40193 TL F 5988.
  • 1 Top View Cascading Packages TL F 5988.
  • 2 C1995 National Semiconductor Corporation TL F 598.

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Other Datasheets by National Semiconductor (now Texas Instruments)

Part Number Description
CD40192BC Synchronous 4-Bit Up/Down Decade Counter
CD40193BC Synchronous 4-Bit Up/Down Decade Counter
CD40193BM 4-Bit Up/Down Binary Counter
CD4019BC Quad AND-OR Select Gate
CD4019BM Quad AND-OR Select Gate

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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CD40192BM CD40192BC Synchronous 4-Bit Up Down Decade Counter CD40193BM CD40193BC Synchronous 4-Bit Up Down Binary Counter February 1988 CD40192BM CD40192BC Synchronous 4-Bit Up Down Decade Counter CD40193BM CD40193BC Synchronous 4-Bit Up Down Binary Counter General Description These up down counters are monolithic complementary MOS (CMOS) integrated circuits The CD40192BM and CD40192BC are BCD counters while the CD40193BM and CD40193BC are binary counters Counting up and counting down is performed by two count inputs one being held high while the other is clocked The outputs change on the positive-going transition of this clock These counters feature preset inputs that are enabled when load is a logical ‘‘0’’ and a clear which forces all outputs to ‘‘0’’ when it is at logical ‘‘1’’ The c