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CGS64LCT800 - Low Skew PLL 1-to-8 CMOS Clock Driver

Download the CGS64LCT800 datasheet PDF. This datasheet also covers the CGS64C800 variant, as both devices belong to the same low skew pll 1-to-8 cmos clock driver family and are provided as variant models within a single manufacturer datasheet.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (CGS64C800-NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

General Description

Q ,!') These minimum skew clock drivers are designed for Clock Generation and Support (CGS) applications operating at high frequencies utilizing a phase lock loop.

The phase lock loop allows for outputs to lock-on to either SyncLO or SyncL1 inputs, which could be operating at different frequencies.

This product is ideal for applications requiring clock synchronization and distribution of either on or off board components.

Overview

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