CR16HCS5 Datasheet PDF - National Semiconductor Family of 16-bit CAN-enabled CompactRISC Microcontrollers Specs

CR16HCS5 - Family of 16-bit CAN-enabled CompactRISC Microcontrollers

This page provides the datasheet information for the CR16HCS5, a member of the CR1 Family of 16-bit CAN-enabled CompactRISC Microcontrollers family.

Datasheet Summary

Description

plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost.

The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz.

Features

and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architecture while retaining the advantages of a traditional Com- Block Diagram Fast Clk Slow Clk.
CR16CAN FullCAN 2.0B Clock Generator Power-on-Reset CR16B RISC Core Processing Unit Core Bus Peripheral Bus Controller 64k-Byte Flash Program Memory 3k-Byte RAM 2176-Byte 1.5k-Byte ISP EEPROM Memory Data Memory Interrupt Control Power Management Timing and Watchdog Periphe.

Datasheet Details

Part number	CR16HCS5
Manufacturer	National Semiconductor
File Size	722.30 KB
Description	Family of 16-bit CAN-enabled CompactRISC Microcontrollers
Datasheet	CR16HCS5 Datasheet
Additional preview pages of the CR16HCS5 datasheet.

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Full PDF Text Transcription

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CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers January 2002 CR16HCS5/CR16HCS9/CR16MAR5/CR16MAS5 CR16MAS9/CR16MBR5/CR16MCS5/CR16MCS9 Family of 16-bit CAN-enabled CompactRISC Microcontrollers 1.0 General Description plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz. The device contains a FullCAN class, CAN serial interface for low/high speed applications with 15 orthogonal message buffers, each supporting standard as well as extended message identifiers.

Published: Mar 23, 2005 |