CR16HCS5 Datasheet | National Semiconductor

Description plex Instruction Set puter (CISC): pact code, onchip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz. The device contains a Full CAN class, CAN serial interface for low/high speed applications with 15 orthogonal message buffers, each supporting standard as well as extended message identifiers. The family of 16-bit pact RISC™ microcontroller is based on a Reduced Instruction Set puter (RISC) architecture. The device operates as a plete microputer with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architecture while retaining the advantages of a traditional - Block Diagram Fast Clk Slow Clk- CR16CAN Full CAN 2.0B Clock Generator Power-on-Reset CR16B RISC Core Processing Unit Core Bus Peripheral Bus Controller 64k-Byte Flash Program Memory 3k-Byte RAM 2176-Byte 1.5k-Byte ISP EEPROM Memory Data Memory Interrupt Control Power Management Timing and Watchdog Peripheral Bus I/O µWire/SPI 2x USART ACCESS bus 4x VTU 2x MFT 12-ch 8-bit A/D MIWU 2 Analog parators Please note that not all family members contain same peripheral modules and features . TRI-STATE® is a registered trademark of National Semiconductor Corporation. ©2001 National Semiconductor Corporation .national. Table of Contents 1.0 2.0 3.0 General Description - - - - - - 1 Features - - - - - - - . . . . 3 Device Overview -...