CR16MAR5 Description
plex Instruction Set puter (CISC): pact code, onchip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz.
CR16MAR5 Key Features
- Block Diagram
- 1 Features
- 3 Device Overview
- 5 3.1 CR16B CPU Core
- 5 3.2 Memory
- 5 3.3 Input/Output Ports
- 5 3.4 Bus Interface Unit
- 5 3.5 Interrupts
- 5 3.6 Multi-Input Wake-up
- 6 3.7 Dual Clock and Reset