CR16MBR5 - Family of 16-bit CAN-enabled CompactRISC Microcontrollers

This page provides the datasheet information for the CR16MBR5, a member of the CR1 Family of 16-bit CAN-enabled CompactRISC Microcontrollers family.

Product Overview

National Semiconductor

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Datasheet Details

Part number	CR16MBR5
Manufacturer	National Semiconductor
File Size	722.30 KB
Description	Family of 16-bit CAN-enabled CompactRISC Microcontrollers
Datasheet	CR16MBR5 Datasheet
Additional preview pages of the CR16MBR5 datasheet.

CR16MBR5 Product details

Description

plex Instruction Set Computer (CISC): compact code, onchip memory and I/O, and reduced cost.

The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 25 million instructions per second (MIPS) at a clock rate of 24 MHz.

Features

and low power consumption resulting in decreased system cost. The device offers the high performance of a RISC architecture while retaining the advantages of a traditional Com- Block Diagram Fast Clk Slow Clk.
CR16CAN FullCAN 2.0B Clock Generator Power-on-Reset CR16B RISC Core Processing Unit Core Bus Peripheral Bus Controller 64k-Byte Flash Program Memory 3k-Byte RAM 2176-Byte 1.5k-Byte ISP EEPROM Memory Data Memory Interrupt Control Power Management Timing and Watchdog Periphe.

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Published: Mar 23, 2005 |