Datasheet4U Logo Datasheet4U.com

DP8429 - (DP8428 / DP8429) 1 Megabit High Speed Dynamic RAM Controller/Drivers

Description

The DP8428 and DP8429 1M DRAM Controller Drivers are designed to provide ‘‘No-Waitstate’’ CPU interface to Dynamic RAM arrays of up to 8 Mbytes and larger The DP8428 and DP8429 are tailored for 32-bit and 16-bit system requirements respectively Both devices are fabricated using National’s new oxide

Features

  • Y Y Y Y Y Y Y Y Makes DRAM interface and refresh tasks appear virtually transparent to the CPU making DRAMs as easy to use as static RAMs Specifically designed to eliminate CPU wait states up to 10 MHz or beyond Eliminates 20 discrete components for significant board real estate reduction system power savings and the elimination of chip-to-chip AC skewing On-board ultra precise delay line On-board high capacitive RAS CAS WE and Address drivers (specified driving 88 DRAMs directly) AC specif.

📥 Download Datasheet

Datasheet preview – DP8429

Datasheet Details

Part number DP8429
Manufacturer National Semiconductor
File Size 523.88 KB
Description (DP8428 / DP8429) 1 Megabit High Speed Dynamic RAM Controller/Drivers
Datasheet download datasheet DP8429 Datasheet
Additional preview pages of the DP8429 datasheet.
Other Datasheets by National Semiconductor

Full PDF Text Transcription

Click to expand full text
DP8428 NS32828 DP8429 NS32829 1 Megabit High Speed Dynamic RAM Controller Drivers September 1991 DP8428 NS32828 DP8429 NS32829 1 Megabit High Speed Dynamic RAM Controller Drivers General Description The DP8428 and DP8429 1M DRAM Controller Drivers are designed to provide ‘‘No-Waitstate’’ CPU interface to Dynamic RAM arrays of up to 8 Mbytes and larger The DP8428 and DP8429 are tailored for 32-bit and 16-bit system requirements respectively Both devices are fabricated using National’s new oxide isolated Advanced Low power Schottky (ALS) process and use design techniques which enable them to significantly out-perform all other LSI or discrete alternatives in speed level of integration and power consumption Each device integrates the following critical 1M DRAM controller functions on a sing
Published: |