DP8440 Datasheet | National Semiconductor

Description The DP8440 41 Dynamic RAM Controllers provide an easy interface between dynamic RAM arrays and 8- 16- 32- and 64-bit microprocessors The DP8440 41 DRAM Controllers generate all necessary control and timing signals to successfully interface and design dynamic memory systems With significant enhancements over the DP8420 21 22 predecessors the DP8440 41 are suitable for high performance memory systems These controllers support page and burst accesses for fast page static column and nibble DRAMs Refreshes and accesses are arbitrated on chip RAS low time during refresh and RAS precharge time are guaranteed by these controllers Separate precharge counters for each RAS output avoid delayed back to back accesses due to precharge when using memory interleaving Programmable features make the DP8440 41 DRAM Controllers flexible enough to fit many memory systems Features Y Y Y Y Y Y Y Y Y Y Y 40 MHz and 25 MHz operation Page detection Automatic CPU burst accesses Support 1 4 16 64 Mbits DRAMs High capacitance drivers for RAS CAS WE and Q outputs Support for fast page static column and nibble mode DRAMs High precision PLL based delay line Byte enable for word size up to 32 bits on the DP8440 or 64 bits on the DP8441 Automatic Internal Refresh Staggered RAS-Only refresh Burst and CAS-before-RAS refresh Error scrubbing during refresh TRI-STATE outputs Easy interface to all major microprocessors Block Diagram TL F 11718 - 1 FIGURE 1 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 11718 RRD-B30M75 Printed in U S A DRAM Controller DP8440V-40 DP8440VLJ-40 DP8440VLJ-25 DP8441VLJ-40 DP8441VLJ-25 Maximum Clock Frequency 40 MHz 40 MHz 25 MHz 40 MHz 25 MHz Package Type 84-Pin PLCC 100-Pin PQFP 100-Pin PQFP 100-Pin PQFP 100-Pin PQFP Bus Width Supporting 8 16 32 8 16 32 8 16 32 8 16 32 64 8 16 32 64 Largest DRAM Possible 16 Mbits 16 Mbits 16 Mbits 64 Mbits 64 Mbits Table of Contents 1 0...