DS3883A
Description
The DS3883A is one in a series of transceivers designed specifically for the implementation of high performance Futurebus+ and proprietary bus interfaces.
Key Features
- BTL eliminates settling time delays that severely limit TTL bus performance, and thus provide significantly higher bus transfer rates
- The backplane bus is intended to be operated with termination resistors (selected to match the bus impedance) connected to 2.1V at both ends
- The low voltage is typically 1V
- Separate QVCC and QGND pins are provided to minimize the effects of high current switching noise
- The DS3883A supports live insertion as defined in 896.2 through the LI (Live Insertion) pin
- To implement live insertion the LI pin should be connected to the live insertion power connector
- If this function is not supported the LI pin must be tied to the VCC pin
- The DS3883A also provides glitch free power up/down protection during power sequencing
- The DS3883A has two types of power connections in addition to the LI pin
- They are the Logic VCC (VCC) and the Quiet VCC (QVCC)
