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DS90CR212 - 21-Bit Channel Link

Download the DS90CR212 datasheet PDF. This datasheet also covers the DS90CR212MTD variant, as both devices belong to the same 21-bit channel link family and are provided as variant models within a single manufacturer datasheet.

General Description

The DS90CR211 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams.

A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link.

Key Features

  • n n n n n n n n Narrow bus reduces cable size and cost ± 1V Common mode range (ground shifting) 290 mV swing LVDS data transmission 840 Mbit/s data throughput Low swing differential current mode drivers reduce EMI Rising edge data strobe Power down mode Offered in low profile 48-lead TSSOP package Block Diagrams DS90CR211 DS90CR212 DS012637-27 DS012637-1 Order Number DS90CR211MTD See NS Package Number MTD48 Order Number DS90CR212MTD See NS Package Number MTD48 TRI-STATE ® is a registered t.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (DS90CR212MTD_NationalSemiconductor.pdf) that lists specifications for multiple related part numbers.

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
DS90CR211/DS90CR212 21-Bit Channel Link July 1997 DS90CR211/DS90CR212 21-Bit Channel Link General Description The DS90CR211 transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. The DS90CR212 receiver converts the LVDS data streams back into 21 bits of CMOS/TTL data. At a transmit clock frequency of 40 MHz, 21 bits of TTL data are transmitted at a rate of 280 Mbps per LVDS data channel. Using a 40 MHz clock, the data throughput is 840 Mbit/s(105 Mbyte/s). The multiplexing of the data lines provides a substantial cable reduction.