GENERAL DESCRIPTION
The SCAN921025 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. IEEE 1149.1 features provide the design or test engineer access via a standard Test Access Port (TAP) to the backplane or cable interconnects and the ability to verify differential signal integrity. The SCAN921025 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-todata and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the syn- chronization mode, the Deserializer will establish lock to a signal within specified lock times.
National Semiconductor
