100315 Datasheet | National Semiconductor

Description The 100315 contains four low skew differential drivers, designed for generation of multiple, minimum skew differential clocks from a single differential input. This device also has the capability to select a secondary single-ended clock source for use in lower frequency system level testing. The 100315 is a 300 Series redesign of the 100115 clock driver. Features - low output to output skew (~50 ps) - Differential inputs and outputs - Small outline package (SOl C) - Secondary clock available for system level testing - 2000V ESD protection - Voltage pensated operating range: -4.2V to -5.7V - Military and industrial grades available Ordering Code: See Section 5 Logic Diagram Cl KIN Cl KIN Cl KSEl TCl K Connection Diagram ~--Cl Kl - .--,1" ...._ Cl K 1 ~--Cl K2 """-:r"'-_ Cl K2 ~--Cl K3 - ,r"'-_ Cl K3 ~--Cl K4 - ~"""""-Cl K4 TL/F/l0960-1 SOICand Flatpack Cl KIN VEE Cl Kl 4 Cl K2 5 Cl K2 Vee A TCl K Cl KIN VEE Cl K4 Cl K4 Cl K3 Cl K3 Vee Cl KSEl TL/F/l0960-2 Pin Names Description Cl KIN, Cl KIN Cl K1_4, CLK1-4 TCl K Cl KSEl Differential Clock Inputs Differential Clock Outputs Test Clock Inputt Clock Input Selectt t TCl K and Cl KSEl are single-ended inputs, with internal 50 k O pulldown resistors. Truth Table CLKSEL Cl KIN l...