54AC191 Datasheet | National Semiconductor

Description The ’AC191 is a reversible modulo 16 binary counter. It features synchronous counting and asynchronous presetting. The preset feature allows the ’AC191 to be used in programmable dividers. The Count Enable input, the Terminal Count output and the Ripple Clock output make possible a variety of methods of implementing multistage counters. In the counting modes, state changes are initiated by the rising edge of the clock. Features n n n n n n n ICC reduced by 50% High speed - 133 MHz typical count frequency Synchronous counting Asynchronous parallel load Cascadable Outputs source/sink 24 m A Standard Military Drawing (SMD) - ’AC191: 5962-89749 Logic Symbols Connection Diagrams Pin Assignment for DIP and Flatpack DS100279-1 IEEE/IEC DS100279-3 Pin Assignment for LCC DS100279-2 Pin Names CE CP P0- P3 PL U/D Q0- Q3 RC TC Description Count Enable Input Clock Pulse Input Parallel Data Inputs Asynchronous Parallel Load Input Up/Down Count Control Input Flip-Flop Outputs Ripple Clock Output Terminal Count Output DS100279-4 FACT™ is a trademark of Fairchild Semiconductor Corporation. © 1998 National Semiconductor Corporation DS100279 .national. Functional Description The ’AC191 is a synchronous up/down counter. The ’AC191 is organized as a 4-bit binary counter. It contains four edge-triggered flip-flops with internal gating and steering logic to provide individual preset, count-up and count-down operations. Each circuit has an asynchronous parallel load capability permitting the counter to be preset to any desired number. When the Parallel Load (PL) input is LOW, information present on the Parallel Load inputs (P0- P3) is loaded into the counter and appears on the Q outputs. This operation overrides the counting functions, as indicated in the Mode Select Table. A HIGH signal on the CE input inhibits counting. When CE is LOW, internal state changes are initiated synchronously by the LOW-to-HIGH transition of the clock input. The direction of counting is...