74F174 Datasheet | National Semiconductor

Description The ’F174 is a high-speed hex D flip-flop The device is used primarily as a 6-bit edge-triggered storage register The information on the D inputs is transferred to storage during the LOW-to-HIGH clock transition The device has a Master Reset to simultaneously clear all flip-flops Features Edge-triggered D-type inputs Buffered positive edge-triggered clock Asynchronous mon reset Guaranteed 4000V minimum ESD protection mercial 74F174PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F174DM (Note 2) 74F174SC (Note 1) 74F174SJ (Note 1) 54F174FM (Note 2) 54F174LM (Note 2) J16A M16A M16D W16A E20A Note 1 Devices also available in 13 reel Use Suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9489- 3 TL F 9489 - 1 TL F 9489 - 2 IEEE IEC TL F 9489- 5 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9489 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 50 33 3 Input IIH IIL Output IOH IOL 20 m A b0 6 m A 20 m A b0 6 m A 20 m A b0 6 m A b 1 m A 20 m A D0 - D5 CP MR Q0 - Q5 Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) Outputs Functional Description The ’F174 consists of six edge-triggered D flip-flops with individual D inputs and Q outputs The Clock (CP) and Master Reset (MR) are mon to all flip-flops Each D input’s state is transferred to the corresponding flip-flop’s output following the LOW-to-HIGH Clock (CP) transition A LOW input to the Master Reset (MR) will force all outputs...