74F175 Datasheet | National Semiconductor

Description The ’F175 is a high-speed quad D flip-flop The device is useful for general flip-flop requirements where clock and clear inputs are mon The information on the D inputs is stored during the LOW-to-HIGH clock transition Both true and plemented outputs of each flip-flop are provided A Master Reset input resets all flip-flops independent of the Clock or D inputs LOW Features Y Y Y Y Y Edge-triggered D-type inputs Buffered positive edge-triggered clock Asynchronous mon reset True and plement output Guaranteed 4000V minimum ESD protection mercial 74F175PC Military Package Number N16E Package Description 16-Lead (0 300 Wide) Molded Dual-In-Line 16-Lead Ceramic Dual-In-Line 16-Lead (0 150 Wide) Molded Small Outline JEDEC 16-Lead (0 300 Wide) Molded Small Outline EIAJ 16-Lead Cerpack 20-Lead Ceramic Leadless Chip Carrier Type C 54F175DM (Note 2) 74F175SC (Note 1) 74F175SJ (Note 1) 54F175FM (Note 2) 54F175LM (Note 2) Note 1 Devices also available in 13 J16A M16A M16D W16A E20A reel Use suffix e SCX and SJX Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB Logic Symbols IEEE IEC Connection Diagrams Pin Assignment for DIP SOIC and Flatpak Pin Assignment for LCC TL F 9490 - 1 TL F 9490 - 2 TL F 9490- 5 TL F 9490 - 3 TRI-STATE is a registered trademark of National Semiconductor Corporation C1995 National Semiconductor Corporation TL F 9490 RRD-B30M75 Printed in U S A Unit Loading Fan Out 54F 74F Pin Names Description UL HIGH LOW 10 10 10 10 10 10 50 33 3 50 33 3 Input IIH IIL Output IOH IOL 20 m A b0 6 m A 20 m A b0 6 m A 20 m A b0 6 m A b 1 m A 20 m A b 1 m A 20 m A D0 - D3 CP MR Q0 - Q3 Q0 - Q3 Data Inputs Clock Pulse Input (Active Rising Edge) Master Reset Input (Active LOW) True Outputs plement Outputs Functional Description The ’F175 consists of four edge-triggered D flip-flops with individual D inputs and Q and Q outputs The Clock and Master Reset are mon The four flip-flops will store the state of...