ADC11DL066 Datasheet | National Semiconductor

Description The ADC11DL066 is a dual, low power monolithic CMOS analog-to-digital converter capable of converting analog input signals into 11-bit digital words at 66 Megasamples per second (MSPS), minimum. This converter uses a differential, pipeline architecture with digital error correction and an onchip sample-and-hold circuit to minimize die size and power consumption while providing excellent dynamic performance and a 450 MHz Full Power Bandwidth. Operating on a single 3.3V power supply, the ADC11DL066 achieves 10.3 effective bits and consumes just 686 m W at 66 MSPS, including the reference current. The Power Down feature reduces power consumption to 75 m W. The differential inputs provide a full scale differential input swing equal to 2 times VREF with the possibility of a singleended input. Full use of the differential input is remended for optimum performance. The digital outputs from the two ADCs are available on separate 11-bit buses with an output data format choice of offset binary or two’s plement. To ease interfacing to lower voltage systems, the digital output driver power pins of the ADC11DL066 can be connected to a separate supply voltage in the range of 2.4V to the digital supply voltage. This device is available in the 64-lead TQFP package and will operate over the industrial temperature range of - 40˚C to +85˚C. An evaluation board is available to ease the evaluation process. Features n n n n n Single +3.3V supply operation Internal sample-and-hold Outputs 2.4V to 3.3V patible Power down mode On-chip reference Key Specifications n n n n n n Resolution DNL SNR (f IN = 10 MHz) SFDR (f IN = 10 MHz) Data Latency Power Consumption - Operating - Power Down 11 Bits ± 0.25 LSB (typ) 64 d B (typ) 80 d B (typ) 6 Clock Cycles 686 m W (typ) 75 m W (typ) Applications n n n n n n n Ultrasound and Imaging Instrumentation munications Receivers Sonar/Radar x DSL Cable Modems DSP Front Ends Connection Diagram TRI-STATE ® is a registered trademark...