CLC011 Datasheet | National Semiconductor

Description National’s linear CLC011, Serial Digital Video Decoder, decodes and descrambles SMPTE 259M standard Serial Digital Video datastreams with serial clock into 10-bit parallel words and a corresponding word-rate clock. SMPTE 259M standard parallel data is encoded and scrambled using a 9-bit shift register and is also converted from NRZ to NRZI. The CLC011 restores the original parallel data by reversing the encoding process. The CLC011 also extracts timing information embedded in the SDV data. These reserved code words, known as Timing Reference Signals (TRS), indicate the start and end of each active video line. By decoding the TRS, the CLC011 correctly identifies the word boundaries of the encoded input data. Detection of the TRS reserved codes is indicated by low-true signals at the TRS and End of Active Video (EAV) outputs. The CLC011’s design using current-mode logic (CML) reduces noise injection into the power supply thereby easing board layout and interfacing. The CMOS patible outputs, which feature controlled rise and fall times, may be set for either 3.3V or 5V swings with the VDP and VCP inputs. The CLC011 Serial Digital Video Decoder, CLC014 Adaptive Cable Equalizer and the CLC016 Data Retiming PLL bine to provide a plete Serial Digital Video receiver system. The CLC011 is packaged in a 28-pin PLCC. Features Data decoding and deserializing CLC011B operates to 360Mbps CLC011A operates to 300Mbps Low noise injection to power supplies Single +5V or - 5.2V supply operation Output levels programmable for interface to 5V or 3.3V logic n Low power n Low cost n n n n n n Block Diagram DS100086-1 © 1999 National Semiconductor Corporation DS100086 .national. Connection Diagram DS100086-2 28-Pin PLCC Order Number CLC011ACQ, or CLC011BCQ See NS Package Number V28A Pin Descriptions Name EAV Pin No. 1 Description End of active video flag. For ponent video, a logic low is output for one cycle of the parallel clock every time an EAV timing reference is...