CR16MNS9 Datasheet | National Semiconductor

Description The family of pact RISC 16-bit microcontrollers offer the high performance of a RISC architecture while retaining the advantages of a traditional plex Instruction Set puter (CISC): pact code, on-chip memory and I/O, and reduced cost. The CPU uses a three-stage instruction pipeline that allows execution of up to one instruction per clock cycle, or up to 20 million instructions per second (MIPS) at a clock rate of 20 MHz. The family of pact RISC™ microcontrollers are general-purpose 16-bit microcontrollers based on a Reduced Instruction Set puter (RISC) architecture. The device operates as a plete microputer with all system timing, interrupt logic, flash program memory or ROM memory, RAM, EEPROM data memory, and I/O ports included on-chip. It is ideally suited to a wide range of embedded controller applications because of its high performance, on-chip integrated features and low power consumption, resulting in decreased system cost. Block Diagram Fast Osc Slow Osc CR16B Core Processing Unit Clock Generator Power-on-Reset Core Bus Peripheral Bus Controller 48k Flash Program Memory 2 kbyte RAM 640 Bytes EEPROM Data Memory boot ROM Interrupt Power-Save Control Management (ICU) WATCHDOG Peripheral Bus I/O µWire/SPI Two USARTs Two MFTs A/D MIWU Two Analog parators Real-Time Timer Please note that not all family members contain same peripheral modules and features . TRI-STATE® is a registered trademark of National Semiconductor Corporation. ©2001 National Semiconductor Corporation .national. Table of Contents 1.0 2.0 3.0 General Description - - - - - - 1 Features - - - - - - - . . . . 3 Device Overview - - -...