DM74LS502 Datasheet | National Semiconductor

Description The LS502 is an 8-bit register with the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion plete (CC) signal coincident with storage of the eighth bit An active LOW Start (S) input performs synchronous initialization which forces Q7 LOW and all other outputs HIGH Subsequent clocks shift this Q7 LOW signal downstream which simultaneously backfills the register such that the first serial data (D input) bit is stored in Q7 the second bit in Q6 the third in Q5 etc The serial input data is also synchronized by an auxiliary flip-flop and brought out on QD Designed primarily for use in the successive approximation technique for analog-to-digital conversion the LS502 can also be used as a serial-to-parallel converter ring counter and as the storage and control element in recursive digital routines Features Y Low power Schottky version of 2502 Y Storage and control for successive approximation A to D conversion Y Performs serial-to-parallel conversion Connection Diagram Dual-In-Line Package Logic Symbol TL F 10189 - 1 Order Number DM54LS502J DM54LS502W DM74LS502WM or DM74LS502N See NS Package Number J16A M16B N16E or W16A VCC e Pin 16 GND e Pin 8 Pin Names D S CP QD CC Q0 - Q7 Q7 Description Serial Data Input Start Input (Active LOW) Clock Pulse Input (Active Rising Edge) Synchronized Serial Data Output Conversion plete Output (Active LOW) Parallel Register Outputs plement of Q7 Output TL F 10189 - 2 C1995 National Semiconductor Corporation TL F 10189 RRD-B30M105 Printed in U S A Absolute Maximum Ratings (Note) If Military Aerospace specified devices are required please contact the National Semiconductor Sales Office Distributors for availability and specifications Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range DM54LS b55 C to a125 C DM74LS 0 C to a70 C Storage Temperature Range b65 C to a150 C Note The ‘‘Absolute Maximum Ratings’’ are those values beyond which...