DP83864 Datasheet | National Semiconductor

Description Features The DP83864 is an extremely efficient full featured Quad - IEEE pliant 10BASE-T,100BASE-TX, 1000BASE-T Physical Layer transceiver with integrated PMD sublayers - Adaptive equalization and Baseline Wander p. to support 10BASE-T, 100BASE-TX and 1000BASE-T - IEEE 802.3u Auto-Negotiation and Parallel Detection Ethernet protocols. - Fully auto-negotiates between 1000 Mb/s, 100 Mb/s, The DP83864 contains four integrated ultra low power and 10 Mb/s full duplex and half duplex devices Gigabit Physical layers. It uses advanced 0.18 µm, 1.8 V - 2.5 V/3.3 V MAC interfaces: CMOS technology, fabricated at National’s South Portland, Maine facilities. - IEEE 802.3u MII with programmable bus ordering - IEEE 802.3z GMII with programmable bus ordering The DP83864 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. Each port interfaces - Reduced GMII (RGMII) ver. 1.3 directly to Twisted Pair media via an external transformer. - Serial GMII (SGMII) This device interfaces directly to the MAC layer through the - LED support (Link10, Link100, Link1000, Activity and IEEE 802.3u Standard Media Independent Interface (MII) Duplex indicators); Direct drive LED’s thru management or the IEEE 802.3z Gigabit Media Independent Interface (GMII). It also supports the reduced pin count RGMII (12 - User Programmable Interrupt pins per port) and serial GMII (8 pins per port). - A 25Mhz or 125Mhz oscillator as reference clock input The DP83864 is a fourth generation of Gigabit Physical - PHY level CRC checking on received packets and PHY layer product with field proven architecture and perforlevel CRC generation for test mode transmit packets mance. Its robust performance ensures drop in replace- 292 BGA package ment of existing 10/100M equipment with 10/100/1000M - Power dissipation approximately 1 W / port Networking infrastructure. - 1.8 V CMOS (core & analog); 2.5 V (analog & I/O); 3.3 V Applications is optional for 3.3 V I/O voltage The DP83864 fits...