DS3875 Datasheet | National Semiconductor

Description The DS3875 Futurebus a Arbitration Controller is a member of National Semiconductor’s Futurebus a chip set designed specifically for the IEEE 896 1 Futurebus a standard The DS3875 implements Distributed Arbitration and Distributed Arbitration messages in a single chip The DS3875 interfaces with Futurebus a through the DS3885 BTL Arbitration Transceiver and the DS3884A BTL Handshake Transceiver The DS3885 BTL Arbitration Transceiver incorporates the petition logic needed for the Arbitration Number signal lines The DS3884A BTL Handshake Transceiver has selectable Wired-OR receiver glitch filtering The DS3884A is used for the Arbitration Sequencing and Arbitration Condition signal lines Additional transceivers included in the Futurebus a chip set are the DS3883A BTL 9-bit Data Transceiver and the DS3886A BTL 9-bit Latching Data Transceiver The DS3886A transceiver features edge-triggered latches in the driver which may be bypassed during a fall-through mode and a transparent latch in the receiver The DS3883A transceiver has no latches in either direction The Logical Interface Futurebus a Engine (LIFE) I O Protocol Controller with 64-bit Data Path incorporates the pelled Mode Futurebus a Parallel Protocol The Protocol Controller handles all the handshaking signals between the Futurebus a and the local bus interfaces and incorporates a DMA Controller with built-in FIFOs for fast queueing Features The controller implements the plete requirements of the IEEE 896 1 specification as a subset of its features Supports Arbitration message sending and receiving Supports the two modes of operation (RESTRICTED UNRESTRICTED) Software configurable double single pass operation slow fast IBA Parking and restricted unrestricted modes of arbitration Built-in 1 ms timer for use in the arbitration cycle User programmable 16 arbitration delays (8 slow and 8 fast) Built-in PLL for accurate delays The PLL accepts clocks from 2...