DS90CF384A Datasheet | National Semiconductor

Description The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL). Also available is the DS90CF364A that converts the three LVDS data streams (Up to 1.3 Gbps throughput or 170 Megabytes/ sec bandwidth) back into parallel 21 bits of CMOS/TTL data (18 bits of RGB and 3 bits of Hsync, Vsync and DE). Both Receivers’ outputs are Falling edge strobe. A Rising edge or Falling edge strobe transmitter (DS90C383A/DS90C363A) will interoperate with a Falling edge strobe Receiver without any translation logic. The DS90CF384A / DS90CF364A devices are enhanced over prior generation receivers and provided a wider data valid time on the receiver output. The DS90CF384A is also offered in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package which provides a 44 % reduction in PCB footprint pared to the 56L TSSOP package. This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces. Features n n n n n n n n n n n 20 to 65 MHz shift clock support 50% duty cycle on receiver output clock Best- in- Class Set & Hold Times on Rx OUTPUTs Rx power consumption < 142 m W (typ) @65MHz Grayscale Rx Power-down mode < 200µW (max) ESD rating > 7 k V (HBM), > 700V (EIAJ) Supports VGA, SVGA, XGA and Dual Pixel SXGA. PLL requires no external ponents patible with TIA/EIA-644 LVDS standard Low profile 56-lead or 48-lead TSSOP package DS90CF384A is also available in a 64 ball, 0.8mm fine pitch ball grid array (FBGA) package Block Diagrams DS90CF384A DS90CF364A Order Number DS90CF384AMTD or DS90CF384ASLC See NS Package Number MTD56 or SLC64A Order Number DS90CF364AMTD See NS Package Number MTD48 TRI-STATE ® is a registered trademark of National Semiconductor Corporation. © 2006 National Semiconductor Corporation DS100870 .national. DS90CF384A/DS90CF364A Absolut...