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DS90CF384A - +3.3V LVDS Receiver

This page provides the datasheet information for the DS90CF384A, a member of the DS90CF364A +3.3V LVDS Receiver family.

Datasheet Summary

Description

The DS90CF384A receiver converts the four LVDS data streams (Up to 1.8 Gbps throughput or 227 Megabytes/sec bandwidth) back into parallel 28 bits of CMOS/TTL data (24 bits of RGB and 4 bits of Hsync, Vsync, DE and CNTL).

Features

  • 1.
  • 2 20 to 65 MHz Shift Clock Support.
  • 50% Duty Cycle on Receiver Output Clock.
  • Best-in-Class Set & Hold Times on RxOUTPUTs.
  • Rx Power Consumption 700V (EIAJ).
  • Supports VGA, SVGA, XGA and Dual Pixel SXGA.
  • PLL Requires no External Components.
  • Compatible with TIA/EIA-644 LVDS Standard.
  • Low Profile 56-lead or 48-lead Packa.

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Datasheet preview – DS90CF384A

Datasheet Details

Part number DS90CF384A
Manufacturer Texas Instruments
File Size 1.44 MB
Description +3.3V LVDS Receiver
Datasheet download datasheet DS90CF384A Datasheet
Additional preview pages of the DS90CF384A datasheet.

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Full PDF Text Transcription

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DS90CF364A, DS90CF384A www.ti.com SNLS040I – JUNE 2000 – REVISED APRIL 2013 DS90CF384A/DS90CF364A +3.3V LVDS Receiver 24-Bit Flat Panel Display (FPD) Link - 65 MHz, +3.3V LVDS Receiver 18-Bit Flat Panel Display (FPD) Link - 65 MHz Check for Samples: DS90CF364A, DS90CF384A FEATURES 1 •2 20 to 65 MHz Shift Clock Support • 50% Duty Cycle on Receiver Output Clock • Best-in-Class Set & Hold Times on RxOUTPUTs • Rx Power Consumption <142 mW (typ) @65MHz Grayscale • Rx Power-down Mode <200μW (max) • ESD Rating >7 kV (HBM), >700V (EIAJ) • Supports VGA, SVGA, XGA and Dual Pixel SXGA. • PLL Requires no External Components • Compatible with TIA/EIA-644 LVDS Standard • Low Profile 56-lead or 48-lead Packages DESCRIPTION The DS90CF384A receiver converts the four LVDS data streams (Up to 1.
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