DS90LV110AT Datasheet | National Semiconductor

Description DS90LV110A is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 200MHz. The DS90LV110A accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE® by use of the enable pin. For more details, please refer to the Application Information section of this datasheet. Features - Low jitter 400 Mbps fully differential data path - 145 ps (typ) of pk-pk jitter with PRBS = 223- 1 data pattern - - - - - - - - - - at 400 Mbps Single +3.3 V Supply Balanced output impedance Output channel-to-channel skew is 35ps (typ) Differential output voltage (VOD) is 320m V (typ) with 100Ω termination load. LVDS receiver inputs accept LVPECL signals LVDS input failsafe Fast propagation delay of 2.8 ns (typ) Receiver open, shorted, and terminated input failsafe 28 lead TSSOP package Conforms to ANSI/TIA/EIA-644 LVDS standard Connection Diagram Block Diagram Order Number DS90LV110ATMT See NS Package Number MTC28 TRI-STATE® is a registered trademark of National Semiconductor Corporation. © 2008 National Semiconductor Corporation .national. Absolute Maximum Ratings (Note 1) If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (VDD-VSS) - 0.3V to +4V LVCMOS/LVTTL Input Voltage - 0.3V to (VCC + 0.3V)...