MM54C32 Datasheet | National Semiconductor

Description Employing plementary MOS (CMOS) transistors to achieve low power and high noise margin these gates provide the basic functions used in the implementation of digital integrated circuit systems The N- and P-channel enhancement mode transistors provide a symmetrical circuit with output swings essentially equal to the supply voltage This results in high noise immunity over a wide supply voltage range No DC power other than that caused by leakage current is consumed during static conditions All inputs are protected against static discharge damage Features Y Wide supply voltage range Y Guaranteed noise margin Y High noise immunity Y Low power TTL patibility Connection Diagram Dual-In-Line Package February 1988 3 0V to 15V 1 0V 0 45V VCC (typ ) fan out of 2 driving 74L Top View Order Number MM54C32 or MM74C32 TL F 5881 - 1 C1995 National Semiconductor Corporation TL F...