SM8213AM - POCSAG Decoder

Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 1.

I O O I O I O I O RF control main output signal RF DC-level adjustment signal PLL setup signal NRZ signal inpu

• a built-in filter. Each of the addresses (max. 7 + 1 dummy = 8) can be assigned to any frame, which also makes the device configurable for many additional services. Each address can be independently set to ON/OFF. Furthermore, built-in buffer memory means decoded information can be fetched in sync with the microcontroller clock, thereby reducing the microcontroller CPU time required. Intermittent-duty method (battery saving (BS) method) control signals, compatible with PLL operation, and Molybdenu.